1. Field of the Invention
The present invention relates to multilevel metal interconnects and, more particularly, to a multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect.
2. Description of the Related Art
A metal interconnect is a semiconductor structure that electrically connects the individual devices on the semiconductor substrate to realize a desired circuit function. Multiple layers of metal are typically needed to provide the required interconnections, with current-generation integrated circuits often employing up to seven layers of metal.
FIG. 1 shows a cross-sectional view that illustrates a conventional multilevel metal interconnect 100. As shown in FIG. 1, interconnect 100, which is formed on a semiconductor substrate 110, has a first layer of isolation material 112 that is formed on substrate 110, and a number of contacts 114 that are formed through isolation layer 112.
In addition, interconnect 100 also has a patterned first metal (metal-1) layer 116 that is formed on isolation layer 112 and contacts 114. Contacts 114 provide an electrical connection with devices formed in substrate 110, such as a source or a drain region of a MOS transistor, while metal-1 layer 116 provides an electrical connection with contacts 114.
In addition, interconnect 100 has a second layer of isolation material 120, known as an intermetal dielectric, that is formed on metal-1 layer 116, and a number of vias 122 that are formed through isolation layer 120. Interconnect 100 also has a patterned second metal (metal-2) layer 124 that is formed on isolation layer 120 and vias 122. Vias 122 provide an electrical connection between patterned metal-1 layer 116 and patterned metal-2 layer 124.
In a similar fashion, interconnect 100 has third and fourth layers of isolation material 130 and 140, respectively. In addition, a number of vias 132 are formed through isolation layer 130 to contact metal-2 layer 124, and a number of vias 142 are formed through isolation layer 140.
Further, interconnect 100 has a patterned third (metal-3) layer 134 and a patterned fourth metal (metal-4) layer 144, respectively, that are formed to provide an electrical connection with vias 132 and 142, respectively. A passivation layer 146 is formed on the layer of fourth isolation material 140 and metal-4 layer 144.
Interconnect 100 is conventionally formed, in part, by depositing a first layer of metal on a first layer of isolation material and the contacts formed through the first layer of isolation material. Following this, the first layer of metal is patterned to form the patterned first metal layer. Next, a second layer of isolation material is formed on the patterned first metal layer and the first layer of isolation material.
Vias are then formed through the second layer of isolation material to form an electrical connection with the first layer of metal. A second layer of metal is then deposited on the second layer of isolation material and the vias, and the process continues until all of the required metal layers have been formed.
The layers of isolation material can be implemented with the same or different materials. Silicon dioxide (SiO2) is commonly used to form each of the isolation layers. Silicon nitride is also commonly used with silicon dioxide, while many current generation processes use dielectric materials with a dielectric constant (K) that is lower than silicon dioxide.
The layers of isolation material provide electrical isolation between the patterned metal layers as well as between metal lines within a given patterned metal layer. The metal-isolation material-metal structure forms a parasitic capacitor which has a capacitance that is partially defined by the dielectric constant (K) of the type of isolation material that is used.
Horizontally adjacent metal lines from a patterned metal layer have a line-to-line capacitance that is partially defined by the layer of isolation material formed between the metal lines. For example, horizontally adjacent metal lines from patterned metal-3 layer 134 have a line-to-line capacitance Ca that is partially defined by the fourth layer of isolation material 140.
In addition, vertically adjacent metal lines have an interlayer capacitance that is partially defined by the isolation material between the metal lines. For example, vertically adjacent metal lines from metal-3 and metal-4 layers 134 and 144, respectively, have an interlayer capacitance Cb that is partially defined by the fourth layer of isolation material 140.
Further, diagonally adjacent metal lines have a cross coupled capacitance partially defined by the isolation material between the metal lines. For example, diagonally adjacent metal lines from metal-3 and metal-4 layers 134 and 144, respectively, have a cross coupled capacitance Cc partially defined by the fourth layer of isolation material 140.
One problem with interconnect 100, particularly in sub-micron integrated circuits, is the RC time delay introduced by interconnect 100. The RC time delay, which is dominated by the line-to-line capacitance Ca, the interlevel capacitance Cb, and the cross coupled capacitance Cc, significantly impacts the speed of the electrical circuit that is formed on the underlying substrate.
U.S. Pat. No. 5,449,953 to Nathanson et al. describe a single level “airbridge” connecting structure for interconnecting monolithic microwave integrated circuits. The manufacturing of these highly specialized structures is, however, not compatible with standard CMOS or bipolar semiconductor device interconnect processing and these structures do not provide a supporting layer beneath the “airbridge.”
U.S. Pat. No. 6,100,590 to Yegnashankaran et al. describe a multilevel metal interconnect where trenches are utilized to reduce the line-to-line and cross-coupled capacitances Ca and Cc. FIG. 2 shows a cross-sectional view that illustrates a prior-art multilevel metal interconnect 200. FIG. 2 illustrates the multilevel metal interconnect taught by U.S. Pat. No. 6,100,590.
Interconnect 200 is similar to interconnect 100 and, as a result, utilizes the same reference numerals to designate the structures that are common to both structures. As shown in FIG. 2, interconnect 200 differs from interconnect 100 in that interconnect 200 has a first trench 210 and a second trench 220.
First trench 210 is formed between horizontally adjacent metal lines from the patterned metal-4 layer 144, and through the fourth layer of isolation material 140. In addition, first trench 210 is formed between horizontally adjacent metal lines from the patterned metal-3 layer 134, and through the third layer of isolation material 130.
Second trench 220 is formed between horizontally adjacent metal lines from the patterned metal-4 layer 144, and through the fourth layer of isolation material 140. In addition, second trench 220 is formed between horizontally adjacent metal lines from the patterned metal-3 layer 134, and through the third layer of isolation material 130.
Second trench 220 is further formed between horizontally adjacent metal lines from the patterned metal-2 layer 124, and through the second layer of isolation material 120. In addition, second trench 220 is also formed between horizontally adjacent metal lines from the patterned metal-1 layer 116.
Trenches 210 and 220 are filled with air, which has a dielectric constant of 1.0. Compared with silicon dioxide, which has a dielectric constant of 3.9, the air in trenches 210 and 220 significantly reduces the line-to-line capacitance Ca and the cross-coupled capacitance Cc.
The contributions of capacitance Ca and capacitance Cc to the total interconnect related capacitance depend on the particular geometry of the integrated circuit layout (e.g. metal line-to-line spacing, thickness of the interconnect dielectric material between metal layers, etc.). For conventional microprocessors, for example, capacitance Ca and capacitance Cc can account for 60–70% or more of the total capacitance related to interconnect 100.
Since the capacitance related to interconnect 100 is the dominant factor affecting the RC time delay in submicron integrated circuits, the presence of trenches 210 and 220 in the interconnect dielectric material reduces the capacitance related to interconnect 100, thereby increasing device speed.